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Data Sheet No. PD60212 revC
IR2520D(S) & (PbF)
ADAPTIVE BALLAST CONTROL IC
* * * * * * * * * *
Features
600V Half Bridge Driver Integrated Bootstrap FET Adaptive zero-voltage switching (ZVS) Internal Crest Factor Over-Current Protection 0 to 6VDC Voltage Controlled Oscillator Programmable minimum frequency Micropower Startup Current (80uA) Internal 15.6V zener clamp on Vcc Small DIP8/SO8 Package Also available LEAD-FREE (PbF)
Packages
8-Lead PDIP IR2520D
8 Lead SOIC IR2520DS
Description
The IR2520D(S) is a complete adaptive ballast controller and 600V half-bridge driver integrated into a single IC for fluorescent lighting applications. The IC includes adaptive zero-voltage switching (ZVS), internal crest factor over-current protection, as well as an integrated bootstrap FET. The heart of this IC is a voltage controlled oscillator with externally programmable minimum frequency. All of the necessary ballast features are integrated in a small 8-pin DIP or SOIC package.
Typical Application Diagram
RSUPPLY DCP2 BR1 MHS F1 L1 CBUS CF RFMIN L2 LF CVCC VCC 1 COM 2 FMIN VB SPIRAL CFL
8 7 6 5
LO MLS HO VS CBS
LRES CSNUB CDC CRES
IR2520D
3
VCO 4
CVCO
DCP1
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1
IR2520D(S)& (PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
VB VS VHO VLO IVCO ICC dVS/dt PD RthJA TJ TS TL
Definition
High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side output voltage Voltage controlled oscillator input current (Note 1) Supply current (Note 2) Allowable offset voltage slew rate Package power dissipation @ TA +25C PD=(TJMAX-TA)RthJA Thermal resistance, junction to ambient 8-Lead PDIP 8-Lead SOIC 8-Lead PDIP 8-Lead SOIC Junction temperature Storage temperature Lead temperature (soldering, 10 seconds)
Min.
-0.3 VB - 25 VS - 0.3 -0.3 -5 -25 -50 -- -- -- -- -55 -55 --
Max.
625 VB + 0.3 VB + 0.3 VCC + 0.3 +5 25 50 1 0.625 125 200 150 150 300
Units
V
mA mA V/ns W
C/W
C
Note 1: This IC contains a zener clamp structure between the chip VCO and COM, which has a nominal breakdown voltage of 6V. Please note that this pin should not be driven by a DC, low impedance power source greater than 6V. Note 2: This IC contains a zener clamp structure between the chip VCC and COM, which has a nominal breakdown voltage of 15.6V. Please note that this supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section.
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Symbol
VBS VS VCC ICC RFMIN VVCO TJ
Definition
High side floating supply voltage Steady state high side floating supply offset voltage Supply voltage Supply current Minimum frequency setting resistance VCO pin voltage Junction temperature
Min.
VCC - 0.7 -1 VCCUV+ Note 3 20 0 -25
Max.
VCLAMP 600 VCLAMP 10 140 5 125
Units
V
mA k V C
Note 3: Enough current should be supplied into the VCC pin to keep the internal 15.6V zener clamp diode on this pin regulating its voltage, VCLAMP.
2
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IR2520D(S) & (PbF)
Electrical Characteristics
VCC = VBS = VBIAS = 14V +/- 0.25V, CLO=CHO=1000pF, RFMIN = 82k and TA = 25C unless otherwise specified.
Symbol
VCCUV+ VCCUVVUVHYS IQCCUV IQCCFLT ICCHF ICCLF VCLAMP
Definition
VCC and VBS supply undervoltage positive going threshold VCC and VBS supply undervoltage negative going threshold VCC supply undervoltage lockout hysteresis UVLO quiescent current Fault mode quiescent current VCC supply current f=85KHz VCC supply current f=35KHz VCC Zener clamp voltage
Min. Typ. Max. Units Test Conditions
11.4 9.0 -- -- -- -- -- 14.4 12.6 10.0 2.7 45 100 4.5 2.0 15.4 13.8 11.0 -- 80 -- -- -- -- A mA V VCC = 10V VVCO=0V VVCO=6V ICC = 10mA V VCC rising from OV
Supply Characteristics
Floating Supply Characteristics
IQBS0 IQBSUV VBSUV+ VBSUVILK Quiescent VBS supply current Quiescent VBS supply current VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold Offset supply leakage current -- -- 7.7 6.8 -- 80 20 9.0 8.0 -- 150 40 10.3 9.2 50 A V V A VCC=10V, VBS=14V VCC=10V, VBS=7V
VB = VS = 600V
Oscillator I/O Characteristics
f(min) f(max) D DTLO DTHO IVCOQS IVCOFS IVCO_5V VVCO_max Minimum oscillator frequency (Note 4) Maximum oscillator frequency (Note 4) Oscillator duty cycle LO output deadtime HO output deadtime IVCO quick start IVCO frequency sweep IVCO when VCO is at 5V Maximum VCO voltage 29.6 67 -- -- -- -- 0.8 -- -- 34 86 50 2.0 2.0 50 1.3 1.1 6 38.2 96 -- -- -- -- 1.7 -- -- kHz % S A V VVCO=0V VVCO=2V VVCO=6V VVCO=0V
Gate Driver Output Characteristics
VLO=LOW VHO=LOW VLO=HIGH VHO=HIGH TRISE TFALL IO+ IOLO output voltage when LO is low HO output voltage when HO is low LO output voltage when LO is high HO output voltage when HO is high Turn on rise time Turn off fall time Output source short circuit pulsed current Output sink short circuit pulse current -- -- -- -- -- -- -- -- COM COM VCC VCC 150 75 140 230 -- -- -- -- 230 120 -- -- mV
nS mA mA
Note 4: Frequency shown is nominal for RFMIN=82k. Frequency can be programmed higher or lower with the value of RFMIN.
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3
IR2520D(S)& (PbF)
Electrical Characteristics
VCC = VBS = VBIAS = 14V +/- 0.25V, CLO=CHO=1000pF, RFMIN = 82k and TA = 25C unless otherwise specified.
Symbol
Definition
Min. Typ. Max. Units Test Conditions
Protection Characteristics
VVCO_RUN CSCF VS_
OFFSET_MAX
VCO voltage when entering run mode Crest factor peak-to-average fault factor Maximum crest factor VS offset voltage VVCO shutdown voltage
-- -- -- 0.74
4.8 5.0 3.0 0.82
-- -- -- 0.91
V N/A V V VS offset = 0.5V
VVCOSD
Minimum Frequency Setting Characteristics
VFMIN VFMINFLT FMIN lead voltage during normal operation FMIN lead voltage during fault mode 4.8 -- 5.1 0 5.4 -- V V
Bootstrap FET
IBS1 IBS2 VB current VB current 30 10 70 20 -- -- mA CBS=0.1uF, VS=0V VBS = 10V
Lead Definitions
Symbol
VCC COM FMIN VCO LO VS HO VB
Description
Supply voltage IC power and signal ground Minimum frequency setting Voltage controlled oscillator input Low-side gate driver output High-side floating return High-side gate driver output High-side gate driver floating supply
VCC 1
8
VB
IR2520D(S)
COM
2
7 HO 6 5
VS LO
FMIN 3 VCO
4
4
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IR2520D(S) & (PbF)
Block Diagram
Bootstrap FET
VCC 1
15.6V
COM 2
IFMIN IVCO IQS
Bootstrap FET Control IFMAX
8
5V UVLO 1V S R1 R2 Q
VB HO VS
7 6
High-Voltage Well VS-Sensing FET
VCC
VCO 4
5.1V T IDT CT 300ns PGEN 0.8V Fault Logic S1 Q S2 R1 R2 Q R Q Q Driver Logic
HIN
Level Shift PGEN
SET RST
Level-Shift FETs
LIN
5
LO
1us blank Averaging Circuit x5
VCC
4.8V
S R
Q Q
UVLO
120uA
5V IFMIN= 5V RRFMIN
FMIN 3
All values are typical
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IR2520D(S)& (PbF)
State Diagram
Power Turned On
VCCUV Mode
1 /2 -Bridge Off IQCC 45 A
VCC < 10V (VCCUV-)
VVCO = 0V VFMIN = 0V
FAULT Mode
/2-Bridge Off V VCO = 0V IQCCFLT 100A VFMIN = 0V
1
VCC > 12.6V (VCCUV+)
Frequency Sweep Mode
Crest Factor > 5.0 (CSCF) or V VCO < 0.82V (VVCOSD)
VFMIN = 5.1V VCO ramps up, frequency ramps down Crest Factor Disabled ZVS Disabled
VCC < 10V (VCCUV-)
VVCO >4.8V (VVCO _RUN)
RUN Mode
VVCO = 6.0V, Frequency = fmin Crest Factor Enabled ZVS Enabled If non-ZVS detected then VVCO decreases and frequency increases to maintain ZVS
All values are typical
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IR2520D(S) & (PbF)
Functional Description
Under-voltage Lock-Out Mode
The under-voltage lock-out mode (UVLO) is defined as the state the IR2520D is in when VCC is below the turn-on threshold of the IC. The IR2520D UVLO is designed to maintain an ultra-low supply current (IQCCUV <80uA), and to guarantee that the IR2520D is fully functional before the high- and low-side output gate drivers are activated. The VCC capacitor, CVCC, is charged by current through supply resistor, RSUPPLY, minus the start-up current drawn by the IR2520D (Figure 1). This resistor is chosen to provide sufficient current to supply the IR2520D from the DC bus. Once the capacitor voltage on VCC reaches the start-up threshold, VCCUV+, the IR2520D turns on and HO and LO start oscillating. Capacitor CVCC should be large enough to hold the voltage at VCC above the VCCUV+ threshold for one half-cycle of the line voltage or until the external auxiliary supply can maintain the required supply voltage and current to the IC.
DCBUS(+)
high-side driver is enabled. During UVLO mode, the high- and low-side gate driver outputs, HO and LO, are both low and pin VCO is pulled down to COM for resetting the starting frequency to the maximum.
Frequency Sweep Mode
When VCC exceeds VCCUV+ threshold, the IR2520D enters frequency sweep mode. An internal current source (Figure 2) charges the external capacitor on pin VCO, CVCO, and the voltage on pin VCO starts ramping up linearly. An additional quick-start current (IVCOQS) is also connected to the VCO pin and charges the VCO pin initially to 0.85V. When the VCO voltage exceeds 0.85V, the quick-start current is then disconnected internally and the VCO voltage continues to charge up with the normal frequency sweep current source (IVCOFS) (Figure 3). This quick-start brings the VCO voltage quickly to the internal range of the VCO. The frequency ramps down towards the resonance frequency of the high-Q ballast output stage causing the lamp voltage and load current to increase. The voltage on pin VCO continues to increase and the frequency keeps decreasing until the lamp ignites. If the lamp ignites successfully, the voltage on pin VCO continues to increase until it internally limits at 6V (VVCO_MAX). The frequency stops decreasing and stays at the minimum frequency as programmed by an external resistor, RFMIN, on pin FMIN. The minimum frequency should be set below the high-Q resonance frequency of the ballast output stage to ensure that the frequency ramps through resonance for lamp ignition (Figure 4). The desired preheat time can be set by adjusting the slope of the VCO ramp with the external capacitor CVCO.
DCBUS(+)
RSUPPLY DCP2
MHS VCC 1 CVCC COM 2 FMIN 3 RFMIN VCO 4 CVCO VCC UVLO Bootstrap FET Driver 15.6V CLAMP Highand Lowside Driver VB 8 HO 7 VS 6 LO 5 MLS CBS CSNUB
TO LOAD
DCP1
RSUPPLY DCP2
DCBUS(-)
LOAD RETURN
MHS VCC 1 CVCC COM 2 FMIN 3 RFMIN VCO 4 CVCO 5 MLS VCO Bootstrap FET Driver 15.6V CLAMP Highand Lowside Driver VB 8 HO 7 VS 6 LO CBS CSNUB
Fig. 1 Start-up circuitry An internal bootstrap MOSFET between VCC and VB and external supply capacitor, CBS, determine the supply voltage for the high-side driver circuitry. An external charge pump circuit consisting of capacitor CSNUB and diodes DCP1 and DCP2, comprises the auxiliary supply voltage for the low-side driver circuitry. To guarantee that the high-side supply is charged up before the first pulse on pin HO, the first pulse from the output drivers comes from the LO pin. LO may oscillate several times until VB-VS exceeds the high-side UVLO rising threshold, VBSUV+ (9 Volts), and the
TO LOAD
DCP1
DCBUS(-)
LOAD RETURN
Fig. 2 Frequency sweep circuitry mode circuitry
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IR2520D(S)& (PbF)
VVCO 6V 4.8V
Run Mode
The IR2520D enters RUN mode when the voltage on pin VCO exceeds 4.8V (VVCO_RUN). The lamp has ignited and the ballast output stage becomes a low-Q, series-L, parallel-RC circuit. Also, the VS sensing and fault logic blocks (Figure 5) both become enabled for protection against nonZVS and over-current fault conditions. The voltage on the VCO pin continues to increase and the frequency deceases further until the VCO pin voltage limits at 6V (VVCO_MAX) and the minimum frequency is reached. The resonant inductor, resonant capacitor, DC bus voltage and minimum frequency determine the running lamp power. The IC stays at this minimum frequency unless non-ZVS occurs at the VS pin, a crest factor over-current condition is detected at the VS pin, or VCC decreases below the UVLO- threshold (see State Diagram).
DCBUS(+)
0.85V Frequency Sweep Mode Freq fmax Run Mode
fmin
RSUPPLY
Fig. 3 IR2520D Frequency sweep mode timing diagram.
VCC 1 CVCC COM 2 FMIN 3 RFMIN VCO 4 CVCO Fault Logic VS Sense VCO Bootstrap FET Driver 15.6V CLAMP Highand Lowside Driver
DCP2
MHS VB 8 HO 7 VS 6 LO 5 MLS CBS CSNUB
TO LOAD
High -Q
Vout Vin
Ignition
DCP1
DCBUS(-)
LOAD RETURN
ea eh Pr t
Fig. 5 IR2520D Run mode circuitry.
Start
Run
Low -Q
Non Zero-Voltage Switching (ZVS) Protection
During run mode, if the voltage at the VS pin has not slewed entirely to COM during the dead-time such that there is voltage between the drain and source of the external lowside half-bridge MOSFET when LO turns-on, then the system is operating too close to, or, on the capacitive side of, resonance. The result is non-ZVS capacitive-mode switching that causes high peak currents to flow in the half-bridge MOSFETs that can damage or destroy them (Figure 6). This can occur due to a lamp filament failure(s),
fmin
fmax
Frequency
Fig. 4 Resonant tank Bode plot with lamp operating points.
8
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IR2520D(S) & (PbF)
lamp removal (open circuit), a dropping DC bus during a mains brown-out or mains interrupt, lamp variations over time, or component variations. To protect against this, an internal high-voltage MOSFET is turned on at the turn-off of HO and the VS-sensing circuit measures VS at each rising edge of LO. If the VS voltage is non-zero, a pulse of current is sinked from the VCO pin (Figures 5 and 6) to slightly discharge the external capacitor, CVCO, causing the frequency to increase slightly. The VCO capacitor then charges up during the rest of the cycle slowly due to the internal current source.
VLO VHO
open circuit (Figure 7). This will cause capacitive switching (hard-switching) resulting in high peak MOSFET currents that can damage them. The IR2520D will increase the frequency in attempt to satisfy ZVS until the VCO pin decreases below 0.82V (VVCOSD). The IC will enter Fault Mode and latch the LO and HO gate driver outputs `low' for turning the half-bridge off safely before any damage can occur to the MOSFETs.
RUN MODE VLO VHO
FAULT MODE
VVS
!
VVS
!
IMLS
!
IL
IMHS
IMLS
!
VVCO Capacitive switching. Hard-switching and high peak MOSFET currents!
IMHS
0.85V
VVCO Too close to resonance. Hard-switching and high peak MOSFET currents! Frequency shifted higher to maintain ZVS.
!
Frequency shifted higher until VCO < 0.82V. LO and HO are latched low before damage occurs to MOSFETs.
!
Fig. 7 Lamp removal or open filament fault condition timing diagram
Fig. 6 IR2520D non-ZVS protection timing diagram.
The frequency is trying to decrease towards resonance by charging the VCO capacitor and the adaptive ZVS circuit "nudges" the frequency back up slightly above resonance each time non-ZVS is detected at the turn-on of LO. The internal high-voltage MOSFET is then turned off at the turn-off of LO and it withstands the high-voltage when VS slews up to the DC bus potential. The circuit then remains in this closed-loop adaptive ZVS mode during running and maintains ZVS operation with changing line conditions, component tolerance variations and lamp/load variations. During a lamp removal or filament failure, the lamp resonant tank will be interrupted causing the half-bridge output to go
Crest Factor Over-current Protection
During normal lamp ignition, the frequency sweeps through resonance and the output voltage increases across the resonant capacitor and lamp until the lamp ignites. If the lamp fails to ignite, the resonant capacitor voltage, the inductor voltage and inductor current will continue to increase until the inductor saturates or the output voltage exceeds the maximum voltage rating of the resonant capacitor or inductor. The ballast must shutdown before damage occurs. To protect against a lamp non-strike fault condition, the IR2520D uses the VS-sensing circuitry (Figure 5) to also measure the low-side half-bridge MOSFET current for detecting an
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IR2520D(S)& (PbF)
over-current fault. By using the RDSon of the external lowside MOSFET for current sensing and the VS-sensing circuitry, the IR2520D eliminates the need for an additional current sensing resistor, filter and current-sensing pin. To cancel changes in the RDSon value due to temperature and MOSFET variations, the IR2520D performs a crest factor measurement that detects when the peak current exceeds the average current by a factor of 5 (CSCF). Measuring the crest factor is ideal for detecting when the inductor saturates due to excessive current that occurs in the resonant tank when the frequency sweeps through resonance and the lamp does not ignite. When the VCO voltage ramps up for the first time from zero, the resonant tank current and voltages increase as the frequency decreases towards resonance (Figure 8). If the lamp does not ignite, the inductor current will eventually saturate but the crest factor fault protection is not active until the VCO voltage exceeds 4.8V (VVCO_RUN) for the first time. The frequency will continue decreasing to the capacitive side of resonance towards the minimum frequency setting and the resonant tank current and voltages will decrease again. When the VCO voltage exceeds 4.8V (VVCO_RUN), the IC enters Run Mode and the non-ZVS protection and crest factor protection are both enabled. The non-ZVS protection will increase the frequency again cycle-by-cycle towards resonance from the capacitive side. The resonant tank current will increase again as the frequency nears resonance until the inductor saturates again. The crest factor protection is now enabled and measures the instantaneous voltage at the VS pin only during the time when LO is `high' and after an initial 1us blank time from the rising edge of LO. The blank time is necessary to prevent the crest factor protection circuit from reacting to a nonZVS condition. An internal averaging circuit averages the instantaneous voltage at the VS pin over 10 to 20 switching cycles of LO. During Run Mode, the first time the inductor saturates when LO is `high' (after the 1us blank time) and the peak current exceeds the average by 5 (CSCF), the IR2520D will enter Fault Mode and both LO and HO outputs will be latched `low'. The half-bridge will be safely disabled before any damage can occur to the ballast components. The crest factor peak-to-average fault factor varies as a function of the internal average (Figure 20). The maximum internal average should be below 3.0 volts. Should the average exceed this amount, the multiplied average voltage can exceed the maximum limit of the VS sensing circuit and the VS sensing circuit will no longer detect crest factor
faults. This can occur when a half-bridge MOSFET is selected that has an RDSon that is too large for the application causing the internal average to exceed the maximum limit.
FAULT MODE
During Run Mode, should the VCO voltage decrease below 0.82V (VVCOSD) or a crest factor fault occur, the IR2520D will enter Fault Mode (see State Diagram). The LO and HO gate driver outputs are both latched `low' so that the halfbridge is disabled. The VCO pin is pulled low to COM and the FMIN pin decreases from 5V to COM. VCC draws micro-power current (I CCFLT) so that VCC stays at the clamp voltage and the IC remains in Fault Mode without the need for the charge-pump auxiliary supply. To exit Fault Mode and return to Frequency Sweep Mode, VCC must be cycled below the UVLO- threshold and back above the UVLO+ threshold.
LO AVG*5 IMLS Inductor saturation
INDUCTIVE SIDE OF RESONANCE
CAPACITIVE SIDE OF RESONANCE
IL
4.6V VVCO
FREQUENCY SWEEP MODE
RUN MODE
FAULT MODE
Fig. 8 Crest factor protection timing diagram
10
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IR2520D(S) & (PbF)
16
50
14
VCCUV+
IQCCUV(uA)
40 30 20 10 0 -25
VCCUV+,-(V
12
10
VCCUV8
6 -25 0 25 50 75 1 00 1 25
0
25
50
75
100
125
Temperature(C)
Temperature(C)
Fig. 9 VCCUV+/- vs TEMP
Fig. 10 IQCCUV vs TEMP VCC=10V, VCO=0V
12
1 00
80
VBSUV+,-(V)
10
VBSUV+
IQBSUV(uA)
75 100 125
60
40
8
VBSUV-
20
6 -25 0 25 50
0 25 0 25 50 75 1 00 1 25
Temperature(C)
Temperature(C)
Fig. 11 VBSUV+/- vs TEMP
Fig. 12 IQBSUV vs TEMP
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11
IR2520D(S)& (PbF)
1 00 90 80
90 80
VVCO=0V
Freq(KHz)
70 60 50 40 30
20 K 40 K 60 K 80 K 100 K 120 K
Frequency(kHz)
70 60 50 40 30 20 1 0 0 25 0 25 50 75 1 00 1 25
VVCO=5V
20 1 0 0 25 0 25 50 75 1 00 1 25
140 K
Temperature(C)
Fig. 13 Frequency vs TEMP REMIN=82K Fig. 14
Temperature(C)
Frequency vs RFMIN vs TEMP VVCO=6V
1 00 93 90 25 80 25 75 1 25 60 50 40 30 20 1 0 0 1 2 3 4 5 6 92 25
Frequency(kHz)
Frequency(kHz))
70
91 90 89 88 87 86
25 75 1 25
12
13
14
15
16
VCO(V)
Temperature(C)
Fig. 15 FREQ VS VVCO vs TEMP VCC=14V
Fig. 16 FREQ VS VCC vs TEMP VVCO=0V
12
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IR2520D(S) & (PbF)
2. 5
2
TDHO
2
18 . 16 .
15 .
TDLO
IVCOFS(uA)
14 . 12 . 1 0. 8 0. 6 0. 4
TD (uS)
1
0. 5 0. 2 0 0 25 0 25 50 75 1 00 1 25 25 0 25 50 75 1 00 1 25
Temperature(C)
Temperature(C)
Fig. 17 DTHO, DTLO vs TEMP VCO=0V
Fig. 18 IVCO_FS vs TEMP
7
1 0 9 8
VVCO_MAX (V)
6. 5
7
VCSCF
6 5 4 3
6
5. 5
2 1 0 0. 2 0 25 50 75 1 00 1 25 0. 4 0. 6 0. 8 1
5 25
VS OFFSET(V)
Temperature(C)
Fig. 19 VVCOMAX vs TEMP
Fig. 20 CSCF vs OFFSET
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13
IR2520D(S)& (PbF)
1 0
15 . 1 25 .
8
VVCO_SD (V)
1 0. 75 0. 5 0. 25 0
6
CSCF
4
2
0 25 0 25 50 75 1 00 1 25
25
0
25
50
75
1 00
1 25
Temperature (C)
Temperature(C)
Fig. 21 CSCF vs TEMP VS_OFFSET=0.5V
Fig. 22 VVCO_SD vs TEMP
6 5
1 00
80
VFMIN(V)
4
IBS1(mA)
25 0 25 50 75 1 00 1 25
60
3 2 1 0
40
20
0 25 0 25 50 75 1 00 1 25
Temperature(C) ( )
Temperature(C)
Fig. 23 VFMIN vs TEMP VCO=0V, RFMIN=82K
Fig. 24 IBS1 vs TEMP
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IR2520D(S) & (PbF)
30
25
IBS2(mA)
20
1 5 1 0
5
0 25 0 25 50 75 1 00 1 25
Temperature(C)
Fig. 26 IBS2 vs TEMP
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15
IR2520D(S)& (PbF)
Case outlines
IR2520D 8-Lead PDIP
D A 5 B
FOOTPRINT 8X 0.72 [.028]
01-6014 01-3003 01 (MS-001AB)
INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00
DIM A b c D
A1 .0040
6 E
8
7
6
5 H 0.25 [.010] A
E
6.46 [.255]
1
2
3
4
e e1 H K L
8X 1.78 [.070]
.050 BASIC .025 BASIC .2284 .0099 .016 0 .2440 .0196 .050 8
1.27 BASIC 0.635 BASIC 5.80 0.25 0.40 0 6.20 0.50 1.27 8
6X
e e1
3X 1.27 [.050]
y
A C 0.10 [.004] y
K x 45
8X b 0.25 [.010]
A1 CAB
8X L 7
8X c
NOTES: 1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE C ONFORMS TO JEDEC OUTLINE MS-012AA.
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006]. 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE.
IR2520DS
16
8-Lead SOIC
01-6027 01-0021 11 (MS-012AA)
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IR2520D(S) & (PbF)
LEADFREE PART MARKING INFORMATION
Part number
IRxxxxxx YWW? ?XXXX
Lot Code (Prod mode - 4 digit SPN code) IR logo
Date code
Pin 1 Identifier ? P MARKING CODE Lead Free Released Non-Lead Free Released
Assembly site code Per SCOP 200-002
ORDER INFORMATION
Basic Part (Non-Lead Free) 8-Lead PDIP IR2520D order IR2520D 8-Lead SOIC IR2520DS order IR2520DS
Leadfree Part 8-Lead PDIP IR2520D order IR2520DPbF 8-Lead SOIC IR2520DS order IR2520DSPbF
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 This product has been qualified per industrial level MSL-3 Data and specifications subject to change without notice. 3/1/2005
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